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The system had the following modules:

• Integrated CPU.
• Memory - RAM, FLASH, MMC, Serial EEPROM.
• LCD and Control - LCD Interface, Backlight, Contrast Controller.
• Glue Logic - Memory Mux Controller, MMC Controller, Plug-in Bays, I/O Write buffers.
• Power Supply - Vehicle Supply, Wall Supply, and Filtering.
• Front Panel.
• Plug-in Bay Interface.
• PC Card Bus - PCMCIA, PC Card Bus.
• I/O Connector ports - USB, Ethernet, Serial, LED, Speaker, Dip-Switch.
• Battery Charger.

We have developed the complete Boot code, and the Initial Program Loader where we initialized all the CPU internals as per the Block Diagram below.

The entire development was done as Cross Development on Windows NT, with GNU compatible Compilers and Debuggers. The Operating System, which was customized, was Lynx OS. We also wrote a driver for the Tundra PCI Bridge chipset, which was used on board.

Hardware

The project involves installing Micro-controller based ODESA (Open Data Exchange System) on each Vending Machine that will establish communication between the Elevators Controller and a Secure Central Server through TCP/IP across Analog Telephone line, ISDN or GSM.

Software

The client side solution will be embedded on the Flash ROM chips on the ODESA that will process the data and transmit it through TCP/IP to the Secure Central Server. The Secure Server side solution will be a web enabled Database that will provide Real-time information, MIS, Alarms, etc. to the user.

Technology

The platform suggested uses the Internet as a Global Medium whereby the service could be provided internationally with suitably located Secure servers that may be leased from any international vendor assuring 24X7 support and sufficient redundancy.

Application

• It provides Real-time data on the Device's status and can trigger messages across Unified Messaging Service Platforms in a desired escalation.
• It also collects the Historical Data of Vending Machine Use, Maintenance, Conditions just before the fault, Fault Analysis, Repair Management, etc.

Processor Specification 80188 High integration 8-bit microprocessor

Integrated Feature set

• Enhanced 8086-2 CPU.
• Clock Generator.
• 2 independent DMA Channels.
• Programmable Interrupt Controller.
• 3 programmable 16 bit timers.
• Programmable memory and peripheral chip select logic.
• Programmable wait state generator.
• Local bus controller.
• 16 bit Internal architecture with 8 bit data bus interface.
• High Performance 16 MHz processor.
• 2MB/sec bus bandwidth interface at 8MHz.
• Direct addressing capability to 1MB of memory and 64KB of I/O.

Processor Block Diagram

Digital Input Specification

• Rated Voltage
  • Nominal - +24VDC
  • Maximum - +38VDC
• Input Voltage
  • Logic 1 - +15VDC to +24VDC
  • Logic 0 - -24VDC to +5VDC
• Input Current at Logic 1 - 8mA at +24VDC and 14mA at +38VDC.
• Input Impedance - 2.2k ohms, approximately.
• Isolation - Optical, > 2.0 kV DC.
• Input over-voltage protection.

Analog Modem Specifications

• Supports standards - CCITT V.22bis, V.22, Bell 212 and Bell 103.
• FCC part 68 approved and DOT CSA CS-03 Part 1 approval.
• UL 1950 and CSA C22.2 950 listed.
• AT Command Structure with Extensions.
• 1500 VAC RMS isolation barrier minimum, 2122V peak surge protection minimum.
• Single 5V operation.
• Low power operation with automatic reduced power stand by mode.
• NVRAM allows storage of custom configurations and telephone numbers.
• Test modes and diagnostics.

Functional Block diagram of Analog Modem

GSM Interface Specifications

The Solution contains all analog and digital GSM baseband processing functions in a single chip. Interface functions and drivers are integrated into the chip to enable auxiliary components such as microphone, speaker, and SIM to connect directly to the chip. A flexible baseband control interface supports a wide range of RF transceiver chipsets, including multi-band operation for E-GSM900, GSM1800, and 1900. An optional built-in PCMCIA interface may be enabled for applications in mobile computing. The Layer 2 & 3 functions include a Phase 2+ GSM protocol stack augmented by the addition of multi-slot packet data capability (GPRS) and multi-slot High-Speed Circuit Switched Data (HSCSD). The Class 12 multi-slot capability allows up to 5 used time-slots, 4 in any one direction. In addition, the use of V.42bis can yield up to a 4-fold increase in data transfer rates. Applications using GPRS and HSCSD may both take advantage of these higher multi-slot speeds. ML2020 processing is centered on the two embedded processor cores, the ARM7TDMI RISC and the OAK DSP. The ARM RISC and supporting hardware perform man-machine interface (MMI) functions, protocol processing, and scheduling of Layer 1 functions, as well as higher application layer processing.

ISDN Interface Specifications

• Single chip ISDN-S/T controller with B and D Channel HDLC support.
• Integrated S/T Interface.
• Full 1.430 ITU S/T ISDN support in TE and NT Mode for 5V Power Supply.
• Independent Read and Write HDLC Channels for 2 ISDN B Channels, one ISDN D Channel and one PCM timeslot.
• B1 and B2 channel transparent mode independently selectable.
• Integrated FIFO for B1, B2, D and PCM.
• FIFO size is 128 Bytes per channel and direction; up to 7 HDLC frames per FIFO.
• H.100 data rate supported.
• Microprocessor interface compatible to Intel Bus.
• Timer with interrupt capability.

OVERVIEW:

The SPA’s Industrial Network Controllers plug directly into 19” rack of the SPAMICRO range of Programmable Controllers. Eight such Network Controllers can be plugged into the same rack, and can be used to connect I/O Devices in the same or different Logical LANs. The Ethernet ports on the controller support direct 10 Base T connections using the RJ-45 Connector or BNC Connector, both of which are available on the same Controller. The controller IP address is stored on the on-board E2PROM and can be modified using the SA25AID programming language available along with the SPAMICRO Programmable Controller. The protocol that is used for communication can be selected as TCP/IP or MODBUS.

SYSTEM ANALYSIS:

The Industrial Network Controller, had to be designed keeping in mind the following aspects -
There were three processors involved in the whole system-   

•  The CSMA / CD controller as per IEEE802.3 Specification.
•  The Industrial Network Controller.
•  The SPAMICRO Programmable Controller.

These three processors had to be controlled, and their execution sequenced suitably, if the software had to work in an optimized manner, and provide the throughput, of 10 Mbps.

DETAILED SPECIFICATION

Industrial Network Controller - 386EX
CSMA/CD Controller - 82595TX
SPAMICRO Programmable Controller - 386EX
Back-plane Bus - SPA Bus
Communication -IEEE802.3 10 Base T
EPROM - 128KB
RAM - 128KB
Dual-Port RAM - 16KB
Protocol - TCP/IP or MODBUS
Operating System - SPA RT Kernel
Compiler - Borland C++ Version 4.0
Assembler - Archimedes Cross - Assembler
Cross Development Done on Windows 95.

SOFTWARE DESCRIPTION

This project involved the Development of the following modules -

SA25AID Programming Package –

This package was made Network Compatible, with addition of communication Function Blocks to program the SPAMICRO Controller for communicating over Ethernet. We also had to develop a User Interface to enter I/O information, to be sent-to / received-from each node on the network. Each node’s IP address could also be configured using the SA25AID package, from where the new node number could be downloaded into, E2PROM storage on the Industrial Network Controller. This application was developed on C++, with a Graphical User-Interface, which could work on DOS, or Windows environment. This Networked SA25AID, could also receive I/O values online from the Programmable Controller, and keep the user updated of the instantaneous values of the I/Os.

SPAMICRO Controller –

The SPAMICRO Controller system program, had to be altered to accept the Industrial Network Controller(s) as a valid Add-on board on its SPA Bus Back-plane. Also it had to communicate with the networked version of SA25AID, and accept the network I/O configuration from the SA25AID. Functionality, had to be added to the SPAMICRO System program, for it to retrieve from / update-to it’s Data-table, I/O values available over the network.


Dual-Port-RAM Interface –

A Dual-port-RAM was used to Interface, and Synchronize the exchange of Data of SPAMICRO Programmable Controller with the Industrial Network Controller. A Complex algorithm for the smooth access of the Dual-port-RAM by two or more Devices was Developed and Implemented, to ensure reliable operation without Deadlocks. This implementation was done with C, with the use of Assembly code for faster access of hardware addresses.

Network Controller -

This performs the most important functions of the Industrial Network Controller. It controls the entry and exit of Data from the system, and interacts with the Intel 82595TX CSMA/CD Controller over a 32KB Dynamic RAM. Data that is put into the Dual-Port-RAM, by the SPAMICRO Programmable Controller, is retrieved, and converted to TCP/IP or MODBUS format, and then sent to the 82595TX, is also done, so as to ensure that communication takes place, limiting collisions. This section was also done in C, with Assembly Code for faster access of Hardware Addresses.

CONCLUSION

This project was implemented in 2 Man Years using 4 Developers. It has been working in several Industrial situations, over a network. Very high data throughput has been achieved in noise intensive applications. This solution has upgraded the SPAMICRO Programmable Controller from being a Stand-alone PLC like controller, to a more functional Distributed Control product. In addition, it has added an open connectivity option to the SPAMICRO Programmable Controller.

OVERVIEW:

•  4 Digital Inputs for Jog Forward, Jog Reverse, Home position, and Hardware stop.
•  4 Digital Output for Drive Disable / Enable, Hardware done, Home, and Spare for any user programmable assignment.
•  1 Encoder input for position feedback.
•  Dual-port-RAM access control is important, as that is the only means of communication between the SPAMICRO Programmable Controller, and the Position Control Module.
•  SA25AID package was configured for a set of function blocks to pass parameters to the Position Control Module.
•  The Pulses from the encoder will give the feedback for both position and direction. The Position Control Module will give control signals like direction, end / stop etc. to the field devices. The velocity reference from the Position Control Module will be given to the speed controller. 
•  All calculations to accomplish Position Control such as counting the encoder pulses, determining the direction of motion, calculating position error and generating velocity signal proportional to position error, are done by the Position Control Module.

DETAILED SPECIFICATION 
Embedded Processor - 80C188
Back-plane Bus - SPA Bus
Operating System - SPA Real-time Kernel
Compiler - Borland C++ Version 4.0
Cross - Assembler - Archimedes 
EPROM - 64KB 
RAM - 128KB
Dual-Port RAM - 2KB
Communication Channel - Rs232C
Digital Inputs - 4 Differential Inputs 
Digital Outputs - 4 Transistor Outputs 
Encoder Input - 1 Quadrature Input
Analog Output - 1 Voltage/Current Output

SOFTWARE SYSTEM DESCRIPTION

The main aspects that were considered were -
Basic Control Algorithm –

• The Programmable Controller will issue every ‘Ta’ milliseconds, a positioning command such as, Start / Move / Stop. 
• Every ‘Tb’ milliseconds, the Position Control Module will read the counter (implemented within its internal registers) which stores the position value from the encoder. 
• Check if, actual position has reached the required End-point position, and then, send the appropriate signal to the Programmable Controller. 
• Based on the instantaneous, desired and actual positions calculate the position error and use it in the specified control algorithm. This will depend on the control approach. The result is routed through the Position Control module, as an Analog Output to the drive speed controller. 

Function Blocks - The function Blocks that were implemented on the Programmable Controller were - 

• Set-point Block - This function Block was the user-interface to configure the Start-point and End-point parameters for motion.  
• Output Block - This function block was the User-interface to configure maximum Acceleration, Deceleration, and System End-point, a check point, if violated, automatic braking will be applied.  
• Synchronize Block - The parameters configured here are Jog Forward, Jog Reverse, and Sync Point, which is the position at which all parameters will be set to Pre-defined values.

CONCLUSION

The Position Control Module provides a necessary compensation, if power failure takes place. The system is able to function within tolerable error limits of 0.01%.

OVERVIEW:

This Development was for the enhancement of SPA Programmable Controller Product-line to support PC Based Control and the IEC1131-3 Specification. The focus was on very high reliability, and redundancy, at the same time providing SPA with a system that was user friendly, and easily configurable for the Mission Critical Process Control situation. Speed was an important aspect to be considered, as, although the controller was a generic one. That could be used in any Process Control Scenario, it was also expected to handle the highly speed sensitive Auto-synchronization, and Turbine Application. The control system had to provide open control. This meant, that, all Protocols, and Bus Interfaces had to be as per some Open Standards. This was possible with the Compact PCI, Back-plane, a Fast Ethernet interface to the PC over SNMP/MODBUS, an IEC1131-3 complaint Soft-Logic tool on the PC and Lon-works, and DeviceNet support for I/Os. The SPA controller could act as a PC based Data Acquisition Box, a Stand-alone Programmable Controller, a Remote I/O node on a Distributed Control Network, or even, a Remote Terminal Unit. 

WHAT DOES ALL THIS INVOLVE

Designing such a System, requires a deep understanding of all the aspects how the processor works and how one can optimize communication by the interface of the above mentioned diverse protocols. In the design of the control system, the following aspects were considered - 

• The Total Volume of Data to be Collected / Stored by the system.
• The total number of I/Os possible with each processor.
• Aspects of Triple Modular Redundancy. 
• Compact PCI Specifications and its Implementations.
• Lon-works, and DeviceNet for open I/O interface.    
• Aspects of Development with the ELAN SC400 Micro Controller from AMD. 
• The On-board Fast-Ethernet Controller from Intel for networking.
• SNMP implementation on Fast Ethernet. 
•  MODBUS Protocol Converter, for Open Industrial Protocol interface.
• Implementation of IEC1131-3 Soft- logic interface.  
•  Soft-modem support over RS232C at 38.4 Kbps.

DETAILED SPECIFICATION 
Embedded Processor - Elan SC400
Back-plane Bus - Compact PCI
Operating System - QNX Version 4.23A
Compiler - WATCOM C/C++ Version 10.6
Cross-Assembler - WATCOM
Flash - 8MB NAND Flash 
RAM - 8MB SIMM
Fast Ethernet Controller - 82596
Field Bus Support - Lon-works, and Device-net.

SOFTWARE SYSTEM DESCRIPTION
The software consisted of the following modules -

Bootable - This was the segment of code that enabled the Control System to Start-up. When the Control System was Powered-up, this segment of code took over, checked for stability of input power, initialized all hardware, and then transferred control to a scheduler, which took over operations. Here we used Assembly Language Code, along with C Code.

Shared Database - This was the Database of I/O values, which was designed to update in 100 microsecond intervals. This Database could also be configured to store only current values, as a Stand-alone system, or log history, as a Remote Terminal Unit. This Database was always mirrored, to provide for redundancy of data. This Database was created in C. 

Scheduler - The scheduler was responsible for the continuous, repeated execution of the whole system. It was responsible for making all the different segments of the system work together in sequence, and for making sure that there was no resource Crunch or Deadlock. This was Developed on C++.  

IEC1131-3 Interpreter - An Embeddable Interpreter as per IEC1131-3 specifications was Developed, and Embedded in the Controller. This Interpreter supports Ladder Logic and Structured Text. This is Developed on C++.                                                  

SNMP Implementation on Fast Ethernet - SNMP based communication interface was Developed to communicate with the PC, which would run IEC1131-3 compliant Soft-logic, or HMI Software, like INTELLUTION, or WONDERWARE, over Fast Ethernet. The Controller used was Intel's 82596. This Development was done on C, with Assembly based initialization, and access of the 82596.

MODBUS Communication - MODBUS Communication Protocol was implemented and embedded in the Controller, as an optional open Protocol of Communication for systems that do not support SNMP. This implementation was done on C. 

Process Control Algorithms - Process Control algorithms such as PID (with Auto-Tuning), Adaptive Control, Predictive control, and Fuzzy Logic were implemented. This implementation was done in C++.

Lon-Works - An interface to connect Lon-Works Devices to the Controller was provided. Access of Data from such Devices to the Embedded Database was streamlined, and optimized.  

DeviceNet - An interface for DeviceNet support was built. Routines were written in C to provide the interface.

Soft-modem - A soft-modem was implemented, and integrated with the Embedded Code, so as to provide Dialup access to the Databases embedded on the controller. This was done in C++. 

Redundancy - Mission Critical Process Control is never complete without a foolproof Methodology of Redundancy. The Coat Hanger Methodology of Database verification was employed in the controller. The inputs and subsequent outputs of each steps of the application program were compared, using a Dual-port-RAM and a reliable operation was ensured. Software locks were provided for access of Dual-port-RAM.

CONCLUSION
The system was Developed in 8 Man Years and was found to afford an output Time-stamping capability of 1 millisecond. The switchover from Main to Redundant Processor took 150 microseconds and the transfer of control was Bump less.